Com-Central.net

Most important, perhaps, PWRficient is not x86-based and therefore avoids direct competition with Intel and AMD. Instead, P. A. Semi licensed IBM's Power Architecture and sees actually IBM, ARM and Freescale as its initial competitors. But Bannon mentioned that the chip could compete with Intel in higher-end cluster applications one day.

So, what does P. A. Semi offer? The PWRficient is said to debut as 65 nm PA6T-1682M model 200 million transistors. The chip design integrates two 2 GHz cores, each with 64 KByte I-cache and 64 KByte D-cache. The cores are connected through an interface named "Connexium" that connects to 2 MByte shared L2 cache. The bandwidth of the interface is 16 GByte in read and write processes. Other components of the SoC include transaction trace memory, peripheral trace memory, as well as the "Envoi" component as I/O protocol engine that covers PCI Express, dual 10 Gbit Ethernet, I/O cache, DMA and offload engines, for example.

For the future, P. A. Semi says, the design is scalable to eight cores, to 2.5 GHz clock speed and up to 8 MByte L2 cache.

The result, apparently, is a PowerPC-based processor that is promised to deliver a performance-per-watt scenario, that is "much superior" to what processors offer today. According to Bannon, the PWRficient's performance-per-watt ratio is "10-15 times" better than what today's mobile processors deliver and "about 3 times better than Intel's future chips." The company says that "typical" power consumption of the 2 GHz dual-core chip is between 5 and 13 watts.